1. Field of the Invention
The present invention relates to an insulated gate semiconductor device and a method for manufacturing the same, and more specifically to an insulated gate bipolar transistor having a built-in diode and a method for manufacturing the same.
2. Background Art
In power electronics for driving motors or the like, an insulated gate bipolar transistor (IGBT) is used as a switching element in the region wherein the rated voltage is 300 V or higher. Normally, a reflux diode is connected to the IGBT in parallel.
FIG. 35 shows the cross-sectional structure of a conventional IGBT. An N+ buffer layer 112 is formed on a collector P layer 5, and an N− layer 1 is formed thereon. On the surface of the N− layer 1, a P base layer 2 wherein a p-type impurity is diffused is selectively formed. On the surface of the P base layer 2, an emitter layer 3 wherein an n-type impurity of a high concentration is selectively diffused is formed. Trenches from the emitter layer 3 to the N− layer 1 are formed; oxide films 7 are formed on the inner walls of the trenches; and gate electrodes 8 composed of polysilicon are formed therein. In the P base layer 2 between the emitter layer 3 and the N− layer 1, a channel along the above-described trenches is formed. An emitter electrode 11 is formed on a part of the region on the surface of the emitter layer 3 and on the region on the surface of the P base layer 2, and a collector electrode 12 is formed on the back face side of the collector P layer 5.
Next, the operation of the IGBT shown in FIG. 35 will be described. First in the structure of FIG. 35, a predetermined collector voltage VCE is supplied between the emitter electrode 11 and the collector electrode 12, and a predetermined gate voltage VGE is supplied between the emitter electrode 11 and the gate electrode 8 to turn the gate on. When the gate is turned on, the channel region is reversed to the n-type, and a channel is formed. Through this channel, electrons are injected into the N− layer 1 from the emitter electrode 11. By the injected electrons, the N+ buffer layer 112 between the collector P layer 5 and the N− layer 1 is forward-biased, and holes are injected into the N− layer 1 from the collector P layer 5. Then, the resistance of the N− layer 1 is significantly lowered, and the current capacity of the IGBT is elevated. As described above, by the injection of holes from the collector P layer 5, the resistance of the N− layer 1 is lowered.
Next, the operation of the IGBT from the on-state to the off-state will be described. In the structure of FIG. 35, the gate voltage VGE supplied between the emitter electrode 11 and the gate electrode 8 in the on-state is made zero or reverse bias to turn the gate off. When the gate is turned off, the channel region reversed to the n-type returns to a P region, and the injection of electrons from the emitter electrode 11 is stopped. Thereby, the injection of holes from the collector P layer 5 is also stopped. Thereafter, electrons and holes having accumulated in the N− layer 1 (N+ buffer layer 112) escape to the collector electrode 12 and the emitter electrode 11, respectively, or recombine to each other and disappear (e.g., refer to Japanese Patent Application Laid-Open No. 2005-101514)